1. Field of the Invention
The invention relates to a method for performing memory accesses. Specifically, embodiments of the invention include a method and apparatus for the parallel execution of address-mapping and page-referencing in a memory controller.
2. Background
A processor in a computer system routinely accesses system memory to retrieve instructions and data, as well as, store instructions and data during the execution of applications, the operating system and all other programs. The processor sends these memory access requests, which may include both read requests and write requests, to a memory controller.
The memory controller makes a determination of the location of requested data for a read operation or the destination for a write operation in the system memory. The memory controller also determines the state of the relevant location in the memory. The memory controller performs address-mapping of an address supplied by the processor or other component requesting the memory access. The address mapping analyzes the input address to determine the rank, bank, row and column of the relevant location in memory. System memory addresses are grouped into ranks, which are subdivided into banks. The banks are organized as a set of rows and columns. The output of the address-mapping process is then used to perform page-referencing. Page-referencing involves a lookup of the state of the relevant location of memory using the rank-bank (a particular rank and bank combination) and row information from the address-mapping process. The page-referencing process determines if a relevant rank-bank is open and if the row is the last accessed row. This information is in turn used to determine if a column access strobe (CAS) command, a row access strobe (RAS) and CAS (RAS-CAS) command sequence or a precharge command (PRE)-RAS-CAS operation needs to be performed to access the relevant portion of memory.
FIG. 1 is a diagram of one embodiment of a conventional address-mapping and page-referencing component 101. The component receives an input address in a first stage and processes it in a multiplexor 103 that separates the rank-bank indicator, the row indicator and column indicator based on selector signals received from a configuration register. In a second stage, the page-referencing process begins with the use of a page table 107 containing the status of the rank-bank including an indicator of whether each rank-bank is dosed or open (e.g., page status bit) and the last accessed row using the rank-bank indicator identified in stage one. The page table 107 input is provided to the multiplexor 105 and the rank-bank indicator is supplied as the selector resulting in an output of the last accessed row and the open/closed status of the rank-bank.
In a third stage, the row indicator derived from the address input in stage one is compared with the last row accessed for the rank-bank, as determined in stage two, by a comparator 109. The output of the comparator 109 (match/no match) is supplied to combinational logic 111 in stage four. The combinational logic 111 generates one of a CAS command, RAS-CAS command sequence and a PRE-RAS-CAS command sequence or indicator based on the comparator input and the open/close rank-bank indicator from stage three. One of these indicators is applied to the memory device along with the rank, bank, row and column indicators and any relevant data (for a write operation) to carry out the memory access request.
Guideline line 113 shows the latency path through the four stages of this component. The length of this path indicates the relative length of time required to complete these four stages and perform this segment of the memory access request. The length of this latency directly contributes to the length of time to carry out the entire memory access request and consequently the speed of memory access in the computer system.